The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure provides a complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation. The present disclosure also provides methods of fabricating such a CMOS structure.
One trend in modern integrated circuit manufacture is to produce semiconductor devices, such as field effect transistors (FETs), which are as small as possible. In a typical FET, a source and a drain are formed in an active region of a semiconductor substrate by implanting n-type or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
Although the fabrication of smaller transistors allows more transistors to be placed on a single substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, the downscaling of n-channel field effect transistors (nFETs) and p-channel field effect transistors (pFETs) may result in a scaled inversion layer thickness (Tiny) being located between the gate dielectric layer and the semiconductor substrate. The prior art scaled Tiny nFETs and pFETs, however, exhibit a shift in threshold voltage and a reduction in electron/hole mobility which, in turn, negatively impact the performance of the scaled Tiny nFET or pFET device.